The manufacture of integrated circuits at very large scale integration (VLSI), or ultra large scale integration (ULSI), requires a large investment in time and resources. Before committing a circuit design to the manufacturing process it is desirable to validate the circuit design.
Validation of a design is the process of examining the behavior of the design implementation in light of the specification for the design. Validation can be done in a variety of ways and includes both static analysis and dynamic analysis techniques. There are currently many computer aided design (CAD) packages that are used specifically for circuit validation, and these packages are generally referred to as electronic design automation (EDA) tools.
In static analysis the circuit is analyzed without input data and time dependent behavior is not considered. For example, a circuit can be modeled as a resistance-capacitance (RC) tree, or sequential elements followed by combinational elements, in order to determine the approximate maximum signal path delays. Static analysis yields maximum delay information and can be used to find gross design violations; however, it has the disadvantage of occasionally reporting violations for circuit paths that are not used in the operation of the circuit because it does not consider the behavior of the circuit with actual input signals. Conventional static timing also has the disadvantage of reporting violations in parts of the circuit that are not of interest (e.g., previously tested portions of the circuit). Static analysis is also unable to account for data-dependent delays or handle certain circuit topologies.
In dynamic analysis a set of input data is generated and the observation of the time dependent behavior of the circuit is observed in response to the input. The application of a set of input data and the observation of the response is called simulation. In simulation, the design implementation is usually expressed in terms of a netlist that is generated from a hardware description language such as VERILOG or VHDL. Of the EDA tools in use, simulators are the most significant in terms of cost and time.
Due to the complexity of VLSI and ULSI circuits, the cost of a fully comprehensive design simulation is prohibitive, and there are tradeoffs between accuracy, speed and coverage. Thus, considerable effort has been focused on finding ways to improve the speed and efficiency of the simulation process.
Simulators spend time in two separate phases: compilation and runtime. Normally, runtime is the more significant of the two, particularly if the design is being analyzed at the gate level rather than the register transfer level (RTL). Since runtime typically requires considerably more time than compilation, it is desirable to find methods of compiling the circuit for simulation that will reduce the overall time required for the runtime phase.